70's computers

[ben]

On 10/23/2018 5:26 PM, Guy Sotomayor Jr via cctalk wrote:
> 
> 
>> On Oct 23, 2018, at 4:08 PM, Noel Chiappa via cctalk <cctalk at classiccmp.org> wrote:
>>
>>> From: Ben Bfranchuk
>>
>>> I just can't find a clean simple design yet. ...
>>> The PDP 11 is nice machine, but I am looking  for simpler designs
>>> where 16K words is a valid memory size for a OS and small single user
>>> software.
>>
>> There was a recent discussion about code density (I forget whether here, or
>> on TUHS), and someone mentioned this paper:
>>
>>   http://web.eece.maine.edu/~vweaver/papers/iccd09/iccd09_density.pdf
>>

I took a peek at PDF, before supper. "Benchmark in C"
That implies byte addressing, so that is not good test for older 
machines with word adressing only.

>> which shows that for a combo of benchmarks, the PDP-11 had the densest code
>> out of all the ones they looked at. (They didn't look at the PDP-8, but I
>> suspect that since it's a single-address design, it's almost ceertainly not
>> as dense.)
>>
>> The PDP-11 dates back to the days of core (it went through several generations
>> before DRAM arrived - e.g. the -11/70 originally shipped with core), and given
>> core prices, minimizing code size was pretty important - hence the results
>> above.
>>
>> So if you want to get the most bang out of 16K buck...

Get rid of byte adressing. OK 64K of bytes or 32K words is much the 
same, but we all know in hindsight 64KB is just too small for may 
applications.

>>
>> Not the simplest machine to implement, mind - the -8 is a lot simpler. Which
>> axis is the most important to you?
> 
> For simplicity and reasonable density, you might want to look at J1 (which is
> a Forth CPU).  It has been implemented in 300 lines of Verilog and the entire
> CPU + 16KB of memory fits in a reasonably sized Spartan 3E FPGA (and you
> have space for all of the other “cool” stuff).
> 
> Admittedly, you get to write in Forth which may be a minus for some folks.  ;-)
> 
> I did write a simulator for it (in Forth of course!) but I’m in the process of redoing
> it in C so that I can have multiple threads of execution (for the various devices I
> want to emulate).  For me it was important because I’m using this as the controller
> in an FPGA so I wanted to have a better debug environment for developing the
> code.  ;-)

I use ALTERA FPGA products so I code in ADHL or use TTL macros.
It is not that I understand VERLOG or VHDL, but they are so VERBOSE that 
I don't know just is being defined or compiled.

The FPGA is emulating TTL or 22V10 PAL logic so that I can get a design 
tested before I start laying out PCB's.


> TTFN - Guy
> 
>