M6809E/63C09E databus behavior question

[Jim Brain]

I agree this is very specific, but I thought perhaps someone could help.

As I look at the '09 datasheets, I can't tell when the data lines become 
valid on a write cycle.

I ask because I have created a few projects that place themselves 
between the CPU and the CPU socket (CPLD based).

To play nice with a potentially shared address and databus, my code 
honors the BA and TSC lines on the IC.  If either line is high, as noted 
in the datasheet, I tristate the address and data lines.

Otherwise, the address lines are valid during the entire E cycle.

As for data, it depends on the state of the R/W line.

If R/W is high, the external databus is connected to the CPU databus 
during the entire cycle if TSC and BA are both low.

If R/W is low, I initially set the external data bus according to this 
assign statement:

assign data_ext = (!r_w & e& !(tsc | ba) ? data_09 : 8'bz);

The '09 boots, but certain devices fail to operate.  If I change the 
assign to:


assign data_ext = (!r_w & (e | q) & !(tsc | ba) ? data_09 : 8'bz);

or

assign data_ext = (!r_w& !(tsc | ba) ? data_09 : 8'bz);

The devices begin working.

Either of the modified equations works, but I don't know if can safely 
place data on the external databus during the entire cycle, like the 
address lines, or if I need to be off the bus for some small portion of 
the cycle.  I was hoping the datasheets could help, but I am missing the 
key portion of the timing diagrams.

I hope someone can enlighten me.  I have the system working, I just want 
to make it as good as possible.

Jim


-- 
Jim Brain
brain at jbrain.com
www.jbrain.com