M6809E/63C09E databus behavior question

[Eric Smith]

On Thu, May 31, 2018 at 10:48 PM, Jim Brain via cctalk <
cctalk at classiccmp.org> wrote:

> I agree this is very specific, but I thought perhaps someone could help.
>
> As I look at the '09 datasheets, I can't tell when the data lines become
> valid on a write cycle.
>

In the MC68x09E datasheet, that is parameter 20, which is the from the
rising edge of the Q clock to write data valid. In the HD68x09E datasheet,
it is t(DDW)

MC6809E:  maximum 200ns
MC68A09E:  maximum 140ns
MC68B09E: maximum 110ns
HD63B09E: maximum 110ns
HD63C09E: maximum 70ns

Note that these times guarantee that as long as your clock timing is within
specifications, the write data will be valid at least slightly before the
rising edge of the E clock.

If you need to know the specifically how much time the write data is valid
before the rising edge of the E clock, you can derive that based on the
clock frequency you're using.

Either of the modified equations works, but I don't know if can safely
> place data on the external databus during the entire cycle, like the
> address lines, or if I need to be off the bus for some small portion of the
> cycle.  I was hoping the datasheets could help, but I am missing the key
> portion of the timing diagrams.
>

If you drive the data bus too soon after the falling edge of E, you might
have contention with whatever chip was driving the data bus in the previous
cycle.

I have never seen a design using a 6800/6500-style bus that depends on the
write data being valid more than a few ns before the rising edge of E
(phase 2 for 65xx).

Best regards,
Eric