Another DCJ11 oddity

[Eric Smith]

On Tue, Jul 10, 2018 at 1:38 PM, Noel Chiappa via cctalk <
cctalk at classiccmp.org> wrote:

>     > From: Jerry Weiss
>     > In addition to above, there is a bypass cache bit in the PDR (section
>     > 1.5.6.2) for finer control.
>
> Yes, I only found that out last night (or maybe I saw it on a previous scan
> of the manual, but its importance didn't register). The -11/70 doesn't have
> that! Very useful for my application (a memory tester program)...
>

IIRC, there are jumpers in the 11/70 that can be used for cache bypass. It
wasn't considered necessary or useful for normal system operation. Software
control of cache bypass was added to the KB11-Cm used in the ill-fated
PDP-11/74 multiprocessor system. Also the KB11-Cm had interlocked ASRB like
the J11; the memory bus from the cache to the MKA11 multiport memory had an
additional signal to interlock the ASRB read/modify/write. Unfortunately
there's no public documentation on the KB11-Cm or the MKA11 from which to
inspect the details. I think the KB11-Cm _might_ have forced ASRB
instructions to always bypass the cache, to avoid the need to dedicate an
entire uncached page to semaphores, but I'm not certain.