Foonlies

[Paul Koning]

> On Jan 31, 2018, at 7:20 PM, Mark Linimon via cctalk <cctalk at classiccmp.org> wrote:
> 
> On Wed, Jan 31, 2018 at 10:00:53AM -0800, Chuck Guzis via cctalk wrote:
>> An all-ECL redesign (details escape me) resulted in no appreciable
>> improvement in performance.
> 
> But I'm sure the local power company appreciated the extra revenue they
> got from it.
> 
> (I recently donated the little chunk of ECL logic I had back to Rice
> University, where it came from lo those many years ago.  Even by the
> time they were building their "fast" computer in 1970, 74S was already
> starting to catch up.)

Then again, DEC Western Research Lab in the mid 1980s did an interesting project to do a full custom single ECL chip implementation of a MIPS (or Alpha?) CPU, intended to run at 1 GHz.  The CAD system they built for this was quite interesting, as were bits of key technology like a heat pipe based chip cooling setup, possibly the first such device.  It wasn't finished (the ECL fab shops kept going out of business faster than the CAD team could tweak the design rules in the tools) but some neat stuff came out of it, in internal reports only unfortunately.

	paul