Core memory emulator using non volatile ram.

[Guy Sotomayor Jr]

> On Dec 17, 2018, at 10:52 AM, Noel Chiappa via cctalk <cctalk at classiccmp.org> wrote:
> 
>> From: Paul Koning
> 
>> For that matter, core memory details such as destructive read weren't
>> visible to the CPU
> 
> Umm, not quite. If you'd said 'core memory details such as destructive read
> weren't visible to the _program_', you'd have been 100% correct.
> 
> But as I suspect you know, just overlooked, most (all?) of the -11 CPU's do
> use 'read-modify-write' cycles on the bus (DATIP in UNIBUS terms, DATIO in
> QBUS) where possible precisely for the benefit of core memory with its
> destructive readout. (And there's some hair for interlocking the multiple
> CPU's on the -11/74 which I don't recall off the top of my head.)
> 
> And I have a vague memory of something similar on other early DEC machines;
> probably some -8 models.

But it does *no* harm if the underlying memory does *not* have a destructive
read-out.  Otherwise all of those (even DEC branded) MOS memory boards
wouldn’t work.  ;-)

The DATIP and friends were an optimization implemented in the bus protocol
to allow for it to take advantage of the behavior of core.  However, nothing
breaks if the memory doesn’t implement a destructive read-out.

TTFN - Guy