Core memory emulator using non volatile ram.

[Chris Elmquist]

On Sunday (12/16/2018 at 10:40PM -0800), Chuck Guzis via cctalk wrote:
> On 12/16/18 11:21 AM, Paul Koning wrote:
> 
> > If you simply want non-volatile memory, the obvious answer is SRAM with battery backup and a small FPGA to do the interfacing.
> 
> I proposed nvRAM - CMOS SRAM backed by cell-for-cell flash.  Loads SRAM
> from flash on power-up and stores into flash at power-down.  All that's
> needed is a capacitor to extend the power-down cycle a bit.
> 
> Very fast, available in 8 to 32-bit wide architectures, up to 16Mbit per
> package.
> 
> Claims to be guaranteed for 1M power cycles and doesn't require a battery.

These are pretty neat.  Took me a bit to find an example.  They like to
call it "NvSRAM",

http://www.cypress.com/search/psg/1259#/?_facetShow=ss_ppart_family,ss_pinterface,fs_pdensity_kb_,ss_porganization_x_x_y_,ss_ppackage,ss_pfrequency_mhz_,fs_pspeed_ns_,ss_ptemp_classification,fs_pmin_operating_temp_c_,fs_pmax_operating_temp_c_,fs_pmin_operating_voltage_v_,fs_pmax_operating_voltage_v_,fs_pmin_operating_vccq_v_,fs_pmax_operating_vccq_v_,ss_ptape_reel,ss_pautomotive_qualified,fs_part_price&ss_pinterface=Parallel&fs_pmin_operating_voltage_v_=4.5&fs_pmin_operating_voltage_v_=4.5

which is a typical 32K x 8, 5V device.

The "flash" subsystem is something they call SONOS / QuantumTrap technology.

Takes 8mS to STORE the SRAM to the backing store at power down and 20mS
to RECALL it at power up.

The storage cap is typically 68uF so nothing monster.

Chris
-- 
Chris Elmquist