Core memory emulator using non volatile ram.

[Guy Sotomayor Jr]

> On Dec 15, 2018, at 12:51 PM, Jon Elson via cctalk <cctalk at classiccmp.org> wrote:
> 
> On 12/15/2018 02:45 PM, Anders Nelson via cctalk wrote:
>> Serial flash has an endurance between 10K-100K writes per cell so I think
>> that would break down quickly. Wear-leveling on a serial device would be
>> very slow...
>> 
>> 
> If you intend to use it as main core memory on an old CPU, it will perform VERY poorly, as these memories need to erase a page at a time, and the erase takes milliseconds.  So, writing ONE SINGLE word at a time would invoke an erase cycle each time, slowing it to 1/1000 or worse the speed of the original core memory.  Also, most old CPUs have the memory timing built into the CPU, and can't handle a memory that says "wait”.

Anything FLASH related is quickly going to have issues because of the limited write endurance (1000s of cycles only).  It’s one of the issues that I’m facing with the disk emulators that I’m (trying to) work on.  But it works better there because of the block nature of disks (and I’m using a larger FLASH than necessary to allow for wear leveling plus some really heavy duty error correction…had to refresh myself on error coding theory again).

For core replacements, as I’ve said previously, I prefer MRAM.  They’re as fast as SRAM (35-55ns) with unlimited write endurance, 10+ year data retention and non-volitive (implied by the data retention).  Other than the 3.3v interfaces (and SMT…but almost everything is SMT these days) they’re ideal.

TTFN - Guy