Ideas for a simple, but somewhat extendable computer bus

allison allisonportable at
Fri Nov 17 21:08:29 CST 2017

On 11/17/2017 08:11 PM, Jim Brain via cctalk wrote:
> I'm currently working on a single board computer system, designing
> from scratch partially as an education experience, and also as
> something that might be of interest to others.
> I've laid out the first version of the SBC, and I realize it would
> cost nothing to add an edge connector on the PCB, allowing expansion
> options.  As well, assuming the design has any merit, I can see
> creating one of these SBcs for each family (8080/Z80, 65XX, 68XX, and
> maybe even 16 bit options like TMS9900, 68K, etc.)
 A bus that can accommodate 8/16 and also IO mapped plus memory mapped
peripherals forces a
lot of bus logic or interface logic.  The Current winner that has had
all of those is S100-IEEE-696
and its messy.

The more you try to cram into it the more complex it must be, or the
interface from each SBC is so
constrained they can easily share memory or IO in their natural form
(ex: 16bitter reading 8 bit ram will be slow).

At a minimum make 8 and 16it exclusive or your bus interfacs have high
overhead.   Also take into account that not
all cpus mix well or play well in a multicpu mix.

> However, as the design is not *for* any purpose, and I've never
> designed a bus that could be shared among multiple CPUs, I am
> wondering what bus layout would satisfy the following criteria:
>  * At least enough to support a traditional 8 bit CPU (A0-15,D0-7,
>    RESET, READ/WRITE,CLOCK,INTERRUPTS) with potentially a few more
>    address bits (A16-23)
>  * Minimal number of bus signals to support multi-processors and
>    peripheral cards, but not so few that usefulness is severely crippled
Mread, Mwrite, IOread IOwrite, Eread (early),  Ewrite (Early write)

Then you need a set of bus-request, bus-available signals.

And signals to indicate an 8 or 16 bit read or write (Bhi, Blow) or
for IO and memory...

Interrupts.... each differs and few overlap.

Bottom line if your teaching multi-cpus make the bus as simple as
possible as you then
are not locked to explaining how a 8bitter lives on a 16bit bus or the
other way around.

> * Easy to implement (minimize need for logic that serves to solely
>    handle the bus)
More un-alike stuff on the bus the harder it gets.

>  * (If 16 bit data bus is part of the design): Easy for 8 and 16 bit
>    CPUs and peripherals to share the bus (Maybe this means 16 bit units
>    need to be constrained to 8 bit, not sure)

>  * Works out to a size that I can buy edge connectors cheaply (62 pin
>    .100" connectors are looking like my cheap option at present)

simple 16 data, 24 address likely 6 lines for basic control plus others
your up to 50+ lines and
you may want interleaved grounds and also doubled DC pins for current
capability and more
for multiple voltages.  is 62 enough?   Look at ISA-8 for an answer.

> I looked at home computer busses (Atari, Apple, Commodore, Tandy, TI)
> for a bit of inspiration, but they all seem overly simplistic (not
> horrible, but hate to just punt on the idea).  I also looked at the
> ISA bus and the S-100 bus, but they are a bit overwhelming to me (I
> can grok all the signals, but ensuring they are all responsive seems
> like it will drive more logic be on the PCB jsut to handle the bus,
> and I am trying to keep costs very minimal).

Easy limit the possible mixed set of CPUs. 

   in the 8bit realm that mix well are 8085, Z80, Z180, 8088.   The
other set would be the 6502/6800/6809 group.
  Mixing 6502 and z80 is messy or 6502 with 8088 more of same.

 Adding in the 16bit takes the need for bus translation and timing
between 8bit or 16 bit peripherals.

 Mixing 6500 and z80 are annoying as z80(and 8080, 8085,8088) do IO in
separate space from
memory there 6500/6800/6809 peripheral IO is in memory space.  Sure you
can force the issue with logic
or make the z80 do io in memory space for simple convenience but for
those cpus that is atypical.

The single fastest way to limit cost is limit the possible cpu flavors. 
for example ts fairly trivial to make
8085, 8088 and z80 present similar signals to a common bus.

Most of the machine mentioned were at best single cpu (Atari, Apple,
Commodore, Tandy, TI) and many were
not well executed.  FYI TI 9900 is both 16bit and serial as the LRU
interface is bit addressed serial and
very unique perpierals.

> Thus,
> Is there a bus (or a fraction of a bus standard) that I should
> consider to accommodate the above?  Anyone else interested in this
> idea and in a collaborative mood?

All depends.  IF your trying share peripherals and memory you end up
with S100 or S100 like.  If you trying to
talk to each other than maybe something like GPIB or SCSI (or a flavor
of those) may suit the need.  Or simple
network bus serial or parallel.  The latter can be few in wires but
imposes a protocal to talk from A to B
and may make putting memory (not mass storage) in it awkward.

I did this years ago with 8085/z80/8088 and that ended up sorta like a
simplified bus not unlike ISA-8 (PC xt)
with lines to signal bus master request and ack, plus a interrupt system
tht could be shared (daisy chain or not).
Later I added 8749 cpus as smart IO and found it worked if I created a
false address space for the limited 8749
(8049 can only address 4K rom space and 256bytes ram or IO space) but
the timing and other aspects worked ok.

Busses like PDP-11 (Unibus or Qbus) are DEC unique and have high logic
overhead to talk or even listen.
Also PDP11 had memory mapped IO in a reserved space (BBS7 or any address
with 15/14/13=1) it was also
unmapped space when using MMU.   S100 was primitive and even 696 didn't
make it clean(crosstalk and
ringing issues) though it you used different connector and layout it can
be a model as it addresses
everything but at a price.  Multibus can be 8 or 16 bit but is skewed to
Intel or intel like (z80) cpus and
not unlike ISA-8/16 save for cleaner interrupt implementation (PCs broke

I leave out system specific buses like Exorbus(6800 68000), STDbus(z80),
and a few others unique to a CPU.
Generally after ISA bus (PC XT and AT) PC buses are CPU specific and unique.

Bottom line if ISA-8 is to much then your conditions are contradictory
as anything more is going to
make that look simple. 


> Jim

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