Cross-talk square-wave?

[allison]

On 03/30/2017 06:01 PM, Brent Hilpert via cctalk wrote:
> On 2017-Mar-30, at 1:13 PM, Noel Chiappa via cctalk wrote:
>>> From: Allison
>>> FYI this is the same problem designers hit with DRAMS back 40 years ago.
>> This didn't ring (pun not intended) a bell for me; can you say a bit more?
>>

Early Dram memories were fickle to design and many poor designs got out
with notable consequences.  Examples wer common in the S100 realm and
others too.  The MITS 88-4K was replaced with 88-S4K for that reason it was
that bad and that was using the non-multiplexed 22 pin 4K parts.   The
later 16K
multiplexed 16 pin parts 4116 were worse Tandy TRS80 EI version 1(no buffer)
and 2(buffered cable) leading to the later third try a complete redesign.

The problem was a high capacitance load of many NMos Drams and the
address and
data drive.  The fix was not trivial.  A fairly hard source like a
74S157 (treat as similar
in this case to a voltage source) provides a fast stepped input to a
signal line and
if the line were terminated in its characteristic impedance it would
simply transfer
the signal and preserve waveform.  But an array of 16 DRAM for one
address line
with board and input capacitance looks like a roughly 160pf capacitor to
ground.
Your S157 switches and a step waveform goes from ground to +2.7V (lets say)
and the instantaneous current is rather large with an exponential decay. 
Since the line does not see a termination like its characteristic
impedance or
anything acceptable much of the energy in the pulse is reflected back
and you
see ringing or waveform distortion (depends on length of the line).  So
the then
simple fix was series resistance by experimental (maybe empirical too)
testing
for the best waveform and timing compromise.  Usually this lead to both
re-layout
of the board as when you get 8 or 9 lines doing this the ground gridding
starts
showing  noise too.  In the end its all transmission lines that have
poor termination.

What people often forget at DC and very low frequencies the MOS/CMOS
input are
essentially open circuits.  At high frequencies (pulse rates) its a
capacitor which is
an energy storage device.  Changing that voltage across the cap takes
energy and
time and is not a friendly load by any cable/transmission line.

So putting a SD or even a CF at the end of a ribbon or spectra cable
without adequate
grounds (every other wire or a backplane ground) means the field around
those
wires will couple and be the fields around its neighbours and make
itself known in
the most offensive ways.

For those that have forgotten.... those that forget history will relive it.

*Vonada's Engineering Maxims* are a group of pithy observations about
computer engineering
compiled by Don Vonada, an engineer at DEC
<http://gunkies.org/wiki/DEC>, and reproduced in:

  * C. Gordon Bell, J. Craig Mudge, John. E. McNamara, "/Computer
    Engineering/"

They are:

 1. There is no such thing as ground.
 2. Digital circuits are made from analog parts.
 3. Prototype designs always work.
 4. Asserted timing conditions are designed first; unasserted timing
    conditions are found later.
 5. When all but one wire in a group of wires switch, that one will
    switch also.
 6. When all but one gate in a module switches, that one will switch also.
 7. Every little pico farad has a nano henry all its own.
 8. Capacitors convert voltage glitches to current glitches
    (conservation of energy).
 9. Interconnecting wires are probably transmission lines.
10. Synchronizing circuits may take forever to make a decision.
11. Worse-case tolerances never add - but when they do, they are found
    in the best customer's machine.
12. Diagnostics are highly efficient in finding solved problems.
13. Processing systems are only partially tested since it is impractical
    to simulate all possible machine states.
14. Murphy's Laws apply 95 percent of the time. The other 5 percent of
    the time is a coffee break.



Allison

>>> From: Chuck Guzis
>>> I'll offer a suggestion that if your SD card *must* be a significant
>>> distance from its host
>> Like I said, this is a pre-prototype; on the production units, there will be
>> _no_ cable. The SD socket will be about 1-2" from the FPGA.
>>
>>> From: Dwight Kelvey
>>> this behavior on my PDP-8/e where a 7474 flip flop chip was bad. The
>>> input looked great and the output was "half baked"
>> There's no chip at all on the driving end of the line (just that 470K
>> resistor); we see this with the SD card _unplugged_. And we see the exact
>> same thing on several lines.
>>
>>
>> I'm still not clear, from the discussion, how exactly that nice 'square-wave'
>> interference is happening - could it be capacitative crosstalk? (I'd have
>> thought capacitative cross-talk would be inverted - driving a positive voltage
>> on one 'side' of the 'capacitor' would, I would think, induce an oppposing
>> voltage on the other. But I'm clearly no EE! :-)
> I don't have a full enough picture of the circuit and circumstances to provide a definitive suggestion but, some principles:
>
> Yes, you can 'pass' a square wave through a capacitor - if you couldn't then all the theory behind capacitor-coupled audio amplifiers would be shot.
> The condition required to do so is a long resistor - capacitor time constant relative to the period of the (square) wave:
> 	RC time constant:  t(seconds) = R (ohms) * C (farads)
>
> With a high load R, and large enough C, the current in an R-C series circuit is limited to a tiny level, so it takes a long time for the cap to fully charge.
> For as long as the cap is charging there is current flowing through the R and so you see a voltage drop across the R.
> If you reduce the R value or the C value, at some point you would see the square wave start to distort (the flat top would start to slope down to the right / later in time),
> as the capacitor would start to reach full charge within the period of the square wave and the voltage would start to divide between the C and R.
>
> No, you won't see the inverse polarity, if you drive a + voltage to one side of the cap it sucks the electrons out of the plate on that side, that attracts electrons into the other 'load-side' plate. Those electrons are coming from (being drawn away from) the rest of the load side circuit, here through the R, so you see a + voltage across the R (current is flowing from GND through R into the C, so the RC-junction side of R is more + than the GND side of the R).
>
> Your circuit:
>
> It's not clear C-coupling is what's going on here (the wave shape looks pretty sharp for what I understand of the circuit/layout).
> Notably though, C-coupling would remove any DC bias, but David's screen shot indicates a DC bias on the line.
>
> Is this line currently connected to the FPGA, or is it just the wire and R?
> Perhaps the bias is coming from the FPGA, with C-coupling of the wave via the wire.
> Or perhaps it's all crosstalk from within the FPGA, 'visible' because of the high load R.
>
> If the wire and FPGA pin are connected, separate them (reduce the wire circuit to just the wire and R to GND): see whether the DC bias and/or the square wave disappear.
>
> You could play with reducing the load R value to see what happens to the sig level and wave shape.
>
> (You've mentioned both 470K and 270K for the R, could make a difference to the analysis).
>
>