8085 IO ports

[allison]

On 01/15/2017 01:06 PM, Chuck Guzis wrote:
> On 01/15/2017 09:37 AM, Glen Slick wrote:
>
>
>> In the EPROM binary dump you posted I see code that is doing IN and
>> OUT accesses to the following port locations...
> I've seen that technique used to address a device, such as off-chip
> EEPROM--basically, rather than employ a separate latch for the address
> or map the device into memory space, a block of I/O addresses are used
> to directly access the device.   It seems wasteful--and, as the code
> points out, rather inflexible, as the 8085 only has the
> immediate-operand IN and OUT instructions, but hey, it saves a couple of
> chips.
A good example of that is the NS* MDS controller.  It embeds commands
and data
in the address of access and the content written/read.  While the NS*
was Z80
the controller worked well with 8080 and 8085 and only used a 2k chunk of
space. (E800...EFFFh).

Since the 8085 can address 64K its not a single chip embedded (ep)rom CPU
loosing some space in a controller environment of less than 32K is trivial.

Systems that use memory mapped IO include 6502, 6800, 6809, PDP-11,
and the list goes on.  Works for them.

The instruction set advantage is the data from or to that port can be
masked
or set using BIT(set/clear), AND, OR and other instructions as applicable.
that and a simple latch or D-ff can be very cheap if all you need are a few
bits.

> So, the first thing that I'd look for is what devices on the board can
> be accessed in this fashion.

The instructions for both in and out will likely point to those devices
but beware if the ports are few they may also be partially decoded.

Based on reports so far the board has issues with multiple shorted (blown)
inputs so the lack of transitions suggest down stream failures.  Its most
common when a bolt from the blue (ESD or conducted lightning) has been
the most probable cause.


Allison

> --Chuck
>
>