DEC bus transceivers

[allison]

On 10/24/2016 03:55 PM, David Bridgham wrote:
> On 10/24/2016 12:01 PM, Paul Koning wrote:
>
>> I don't know about the receiver part, but I'd expect that the drivers could very easily be done with a simple transistor circuit.
> Agreed.  However ...
>
>> As for slew rates, unless you have antique transistors, that's not going to be an issue given that you meet the current sink spec; the slew rate of an OC circuit is determined by the system capacitance and the sink current of the driver.
> I think you read this part backwards.  The slew rate requirement is not
> a minimum slew rate but a maximum one.  
It is set by bus loading card and input to devices contribute
capacitance and
pull-up current.   The rule is what you do does not break the system not
individual boards those they must be compliant.
> That is, any modern transistor
> (probably ancient ones too) will be way too fast.  You have to do
> something to slow it down.  
NO no no!  The old 2n706 and 2n3638 (mid 60s silicon parts) are ancient
and still too fast if that were the case.  Its the product of the bus
loading
the saturation characteristics of the device.  In all cases the active low
impedance is less than 20 ohms (much less). 

> Still, I think this one is easily met as
> it's just a series resistor on the gate of the driver MOSFET working
> against the gate capacitance.  Some FPGAs have current limiting on their
> output which may obviate the need for the resistor even.
Actually the Drain of a fet is already loaded with capcitance, look at
their spec's.
Also MOSFETs (trench, hex, or lateral) also have a diode present as well
as a
finite drain resistance.   A series resistor on the gate would seriously
impact
switching time and propagation delay due to Miller capcitance.

The best device is a venerable 2n3904 plus maybe 10 ohms on the collector.
That will easily sink the max 20 loads of the spec with room to spare.

the Qbus is actually harder than Unibus as it can and is extended plus data
and address are multiplex on the same lines which are 120 ohm transmission
lines for speed where the Unibus is 240ohms.  The higher the impedance the
grated the sensitivity to capacitive loading.  Omnibus is a special case
as some
devices can Wire-OR data onto the bus and an active pull-up device would be
unhappy with that.

> The receiver though, that one takes a little more thought.
>
>
Now the input is a device with hysteresis and there are plenty of TTL
devices
that fit in that space and would do well. MOS/CMOS is not god as it high
input
Capacitance and a sensitive to latchup (negative spike from the lines
ringing).

The DEC 8xxx part is like a 7438 for outgoing and 7414 for incoming is the
inversion is wrong there are compliments.   That would be one transceiver
in the package.

My sources include the DEC semiconductor data manual and the Omni/Uni/Q/bus
interfacing manuals.  Most in several editions over time.  That and
prints for
everything I own thanks to Mill Repro.  This information is part of the
design
toolkit.


Allison