ISO: PDP-11/40 LTC and Stack Limit options

[Josh Dersch]

On Tue, Nov 22, 2016 at 7:48 AM, Noel Chiappa <jnc at mercury.lcs.mit.edu>
wrote:

>     > It's possible that they didn't bother wiring NPG to that slot, but
> sent
>     > it directly to the NPG pin on the 'UNIBUS out' connector
>
> Sho'nuff; the 11/40 prints indicate (pg. 86) that "BUS NPG" goes directly
> from
> C07P2 ("Source" - you can see the generation on print K4-5, pg. 62, lower
> right side), to A09U1 (NPG on the UNIBUS Out connector), do not pass
> through
> SPC slot 9, do not collect a grant.
>
> I dunno about any other oddities you're seeing, but I think this one is
> solved. :-)
>
>         Noel
>

Interesting.  I'll have to look tonight and see if the same is true for
other bus grants -- I can run the system with no grant continuity card at
all in slot 9 and everything works.  Which seems strange to me.

I went through and cleaned the edge connectors on all of the boards,
grants, and UNIBUS jumpers, and I went through the CPU set to make sure all
jumpers (etc.) are in the right place for running without an MMU, EIS, LTC,
Stack Limit, etc.  I now have the system booting XXDP (from a SCSI2SD via
the SCSI controller) and things are mostly sane.  Occasionally the
diagnostics start trapping to 10 (reserved instruction trap) so something's
amiss but I didn't have time last night to dig into things.

I did find out why there was that wire missing on the backplane; the KW11-L
requires a wire (carrying one of the bus grant signals) be removed from
slot 3.  My machine is a bit of a mongrel -- the CPU set that it came with
was not original to the machine, so nothing matches up... but things seem
to be rectified now.  Just need to solve the slot 9 mystery and work on
getting diagnostics to pass more reliably.

Thanks,
Josh