Reproduction micros

[Guy Sotomayor Jr]

> On Jul 25, 2016, at 1:34 PM, Sean Conner <spc at conman.org> wrote:
> 
> It was thus said that the Great Peter Corlett once stated:
>> 
>> Unsurprisingly, the x86 ISA is brain-damaged here, in that some instructions
>> (e.g. inc") only affect some bits in EFLAGS, which causes a partial register
>> stall. The recommended "fix" is to avoid such instructions.
> 
>  I'm not following this.  On the x86, the INC instruction modifies the
> following flags: O, S, Z, A and P.  So okay, I need to avoid INC to prevent
> a partial register stall, therefore, I need to use ADD.  Let me check ...
> hmm ... ADD modifies the following: O, S, Z, A, P and C.  So now I need to
> avoid ADD as well?  I suppose I could use LEA but then there goes my bignum
> addition routine ... 
> 
>  -spc (Or am I missing something?)

No Peter is wrong.  All of the modern x86 (at least the Intel CPUs) are OOO
machines with large register files (192 comes to mind) that do register renaming
to map the register(s) used by a particular instruction back into an “architectural”
register (no copy is actually done).  The flags register is also part of the register 
re-naming.  The only stalls occur when one instruction needs the results from an
instruction that hasn’t committed it’s results yet (ie the instruction is still in “flight”).

TTFN - Guy