Reproduction micros

[Cameron Kaiser]

> > It's not.  Peter is talking about a four-bit field in the
> > instructions. You're talking about a six-bit field in the program
> > counter.
> 
> Something that's always bothered me about three-address architectures
> like ARM is why there is the insistence on that scheduling bottleneck,
> the condition code register?  You can see how two-address architectures
> like the x80 and x86 try to get around the problem by having certain
> instructions not modify certain condition code bits

I realize I'm a broken record here, but PowerPC does the same thing. You
have to ask for the bits to be updated (specialized forms like the "dot"
instructions) unless you do an explicit compare instruction, and in many
cases there is a special form to only update a certain set of bits instead
of them all (e.g., "addo" updates overflow but nothing else, "addo." does
overflow and CR bits, "addco." does carry too).

> and even have
> specialized instructions, such as JCXZ, that don't reply on a specific
> condition code.

... bdnz, which decrements CTR and branches if not zero, ...

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  Cameron Kaiser * Floodgap Systems * www.floodgap.com * ckaiser at floodgap.com
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