RISC assembly by hand dammit was Re: Reproduction micros

[Cameron Kaiser]

> > It is true that a few RISC architectures are not very scrutable.
> > Itanium is a notorious example, as are some VLIW machines.  But many
> > RISC machines are much more sane.  MIPS and ARM certainly are no
> > problem for any competent assembly language programmer.
> 
> Indeed.  I've written a modest amount of assembly language code for 
> MIPS, and a bit more for ARM, and I didn't find either at all 
> inscrutable.  Yes, be aware of pipelining and branches and so on, but 
> it's not hard.

I actually find PowerPC assembly very tractable. No branch delay slots,
for example, and reasonable orthogonality. The major thing that's annoying
about it is the "mscdfr" instructions (Means Something Completely Different
For r0 -- addi(s), for example). I've handwritten a great deal of PPC
assembly over the years, and even written a JIT for it.

The late PA-RISC was also a very sane ISA to handwrite assembly in.

SPARC is a little tricky with the register windows, but I guess that's
really no different than writing for any other particular ABI.

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  Cameron Kaiser * Floodgap Systems * www.floodgap.com * ckaiser at floodgap.com
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