Reproduction micros

[Paul Koning]

> On Jul 19, 2016, at 11:04 AM, Peter Corlett <abuse at cabal.org.uk> wrote:
> 
> On Tue, Jul 19, 2016 at 03:30:19PM +0200, Liam Proven wrote:
> [...]
>> There's a hint here, though:
>> https://www.epo.org/learning-events/european-inventor/finalists/2013/wilson/feature.html
> 
> From there, it seems to be saying that the essence of the invention is that the
> ARM ISA is RISC, it is a load-store architecture, and the CPU was pipelined.
> 
> RISC implies a load-store architecture, so that claim is redundant.
> 
> Pipelining is an older idea: the 1979-vintage 68000 does it, and the 1982-vintage
> 68010 even detects certain string/loop instructions in its pipeline and avoids
> re-fetching them from memory when repeating the sequence.
> 
> IMO, it's the predicated instructions that is ARM's special sauce and the real
> innovation that gives it a performance boost. Without those, it'd be just a 32
> bit wide 6502 knockoff.

The article, as usual, talks about a whole bunch of things that are much older than the author seems to know.

RISC, as a term, may come from IBM, but the concept goes back at least as far as the CDC 6000 series.  Pipelining, to the CDC 7600.  And if you equate RISC to load/store with simple regular instruction patterns, you can probably go all the way back to the earliest computers; certainly I can point to early 1950s Dutch computers with load/store single-address instructions.

Finally, predicated instructions are also much older.  It may be that the ARM team reinvented them independently, but you can find them in the Electrologica X-1, which shipped in 1958.  In fact, that machine and its successor X-8 had a significantly more powerful scheme, because the flag controlling the conditional execution could be set on request, rather than being a condition code set by fixed rules.  https://en.wikipedia.org/wiki/Electrologica_X1 has a brief example.

	paul