BC11A paddle boards

[Guy Sotomayor]

> On Jan 27, 2016, at 11:48 AM, Ethan Dicks <ethan.dicks at gmail.com> wrote:
> 
> Sure.  I've been on the support end of selling through-hole kits, but
> I wouldn't want to have to support SMD kits.  I have bought and
> assembled many kits with SMD parts and have enjoyed success, but not
> everyone's builds go smoothly (and even I've had to occasionally fix
> my own screwups).
> 
> And I'm still interested in at least one MEM11A when it gets to that.
> I have this 11/20 that needs some stuffing.
> 

My current plan re:MEM11A is that I’m going to build a prototype using an
FPGA eval board that I already have.  It has a 100pin Hirose connector on
it that brings out a bunch of I/Os.  The “prototype” board will contain all of
the “other” components (FRAM, UARTs, Unibus I/F, etc) that don’t exist on
the eval board.  It will strictly be a bench setup.  This is also why I did the
paddle boards…I need a way to get from the prototype to the Unibus.  ;-)

BTW, I’ve been spending my evenings recently re-writing the simulator in
C to get the functionality that I need to complete the rest of the testing and
coding of the uCode.  I’ve also started writing verilog for the various parts
on the prototype board.  I’m using CPLDs at present but it’s not clear that
with the partitioning I have, that it’ll all fit (right now I have stuff partitioned
into 3 CPLDs just for I/O count).

I’m planning that most of what I do for the prototype board will translate over
to the real board so I won’t have to end up re-writing a lot of code (either
the J1 uCode or verilog) but I expect that there will be some differences
mainly around how things are packaged between FPGA and CPLD(s).

TTFN - Guy