PDP-6s at MIT

[Noel Chiappa]

    > From: Johnny Eriksson

    > From the KI10 and onwards it includes PXCT, since these have the
    > concept of a previous context...
    > Given a pager for the KA10 PXCT would make sense there.

It turns out the KA ITS machines have an instruction that does roughly the
same thing, but it's different. Here's the relevant code fragment from
SYSTEM;ITS >:

  IFN KA10P,[

  SUBTTL STUFF PECULIAR TO KA-10 PROCESSOR

  ;;;PAGING BOX INSTRUCTIONS

  LPM=102000,,	;LOAD PG MEM STATE VECTOR DONT CLR ASSOC MEM
  LPMR= LPM 2,	;CLEAR ASSOC MEM AND LOAD
  SPM= LPM 1,	;STORE PG MEM STATE VECTOR
  LPMRI=LPM 6,	;LOAD PM, CLEAR ASSOC REG, AND CAUSE INTERRUPT
  EXPGNG==4	.SEE UPQUAN	;4 TO TURN ON EXEC PAGING
  XCTR=103000,,	;EXECUTE INSTRUCTION WITH MAPPING CONTROLLED BY AC FIELD
		;VIOLATION CAUSES USER MEM PROTECT INTERRUPT UNLESS INHIBITED
		;VIOLATION ALSO SKIPS BUT THIS IS OF NO CONSEQUENCE UNLESS
		;INTERRUPT IS INHIBITED SINCE PC WILL BE RESET FROM OPC
  XCTRI= XCTR 4,	;XCTR WITH PAGE FAULT INHIBITED (SKIPS ON FAULT)
		; AC FIELD VALUES FOR XCTR AND XCTRI
	XR==1		;MAP READ MAIN OPERAND OF SIMPLE INSTRUCTION (MOVE, SKIPL, HLL)
	XW==2		;MAP WRITE MAIN OPERAND OF SIMPLE INSTRUCTION (MOVEM)
	XRW==3		;MAP READ/WRITE OPERAND OF SIMPLE INSTRUCTION (E.G. IORM)
	XBYTE==3	;MAP BYTE DATA AND BYTE POINTER (ILDB, IDPB)
	XBR==1		;MAP BLT READ
	XBW==2		;MAP BLT WRITE
	XBRW==3		;MAP BOTH OPERANDS OF BLT
		;KA10 PAGING BOX GOES BY WHETHER IT'S A READ OR WRITE (OR RW) CYCLE
		;KL10 PAGING BOX WORKS DIFFERENTLY (SEE BELOW)
		;DO NOT USE MULTI-OPERAND INSTRUCTIONS (DMOVE, PUSH, ETC.) WITH XCTR

The KL and KS are both different (although both use XCTR and XCTRI); the KL
stuff is later down in that file; the special KS instructions are in
KSHACK;KSDEFS > if anyone wants to look at them.

	Noel