Z80 /WAIT signal question

[Eric Smith]

On Fri, Apr 22, 2016 at 3:15 AM, Alexis Kotlowy
<thrashbarg at kaput.homeunix.org> wrote:
> http://kaput.homeunix.org/~thrashbarg/z80.pdf
>
> Looking at this Z80 datasheet (page 20 of the PDF) the timing diagrams
> say the /WAIT signal is sampled on the falling edge of clock state T2.
> If it is active, additional cycles are introdced between T2 and T3. This
> only occurs on op-code fetch, memory reference, input-output and
> interrupt acknowledge cycles.

Thanks, but I'm not convinced by that particular part of the
datasheet. I see where it says:

1)  "The Z80 CPU executes instruction by proceeding through a specific
sequence of operations: *Memory read or write *I/O device read or
write *Interrupt acknowledge"

2)  "Machine cycles can be extended [...] by the insertion of one or
more Wait states by the user."

The first of those statements omits that there can be M cycles which
are of none of those stated cycle types, and are used purely for
internal operation. For example, an ADD HL, BC instruction has three M
cycles, but only the first is a fetch, and the other are internal
operations. The second and third M cycles have seven T-states between
them; probably one of those M cycles has three T-states and the other
has four[*].

I don't see where it says that ONLY the op-code fetch, memory
reference, input-output, and interrupt cycles can be extended, and I
don't see anything in the datasheet or user manual that definitively
states that the second and third M cycle of that 16-bit ADD
instruction can't be extended with wait states by /WAIT being asserted
at the faling edge of T2 of those M cycles.

On the other hand, if someone with personal experience has verified
that internal-only M cycles can't be extended by asserting /WAIT,
that's would answer my question. I'm starting to think that I'll
actually have to kludge up a test circuit to find out.

Best regards,
Eric

[*] I thought at one point I saw Zilog or Mostek Z80 documentation
that gave the specific details of every M cycle of every instruction,
but I can find such a thing at the moment.  :-(