Qbus split I&D?

Johnny Billquist bqt at update.uu.se
Wed Mar 18 08:45:08 CDT 2015

On 2015-03-17 22:45, John Wilson wrote:
> But thinking about how it must work hurts my head.  It's emulating Unibus
> memory at the same time that it's emulating the Unibus map -- i.e. CPU
> accesses (which should be relocated through the onboard PARs) are coming
> over the same bus as DMA (which should be relocated using the Unibus Map).
> How does it know which is which?  Does it need to tap into each model of
> CPU somehow (like how a Microverter gets at MMR3)?  Or is it something
> simple like, BBSY is never asserted by the CPU (not obvious from docs --
> the CPU doesn't need to negotiate to become a master but it still is one
> when it's accessing memory) so if it's on, this is DMA?  And what if there's
> a cache, like the KK11A, that doesn't know about the outboard PARs?

Not sure it's that hard. On the bus, I believe it is visible if this is 
an NPR transaction or not. The Unibus map only applies to NPR transactions.

Addresses originating from the CPU should get the full 22 bit address 
from the MMU.

I was thinking about the Enable/34 again the other day. As others have 
mentioned, there is the question (if I remember right) how the PAR 
registers could be 16 bits (required for 22 bit addressing) when the CPU 
PAR registers only hold 12 bits, and only 12 bits comes out.

One possible other answer might be that the CPU had been modified, so 
that the internal PAR registers were disabled. I found a post that 
possibly suggested something like this on the net.

where the mention that the Enable/34 gives you new PAR registers, but 
keep the PDR registers in the CPU.

But this is still way too little to actually know for sure how things works.


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