Qbus split I&D?

[Eric Smith]

On Mon, Mar 16, 2015 at 6:40 PM, Paul Koning <paulkoning at comcast.net> wrote:
> Interesting notion.  With a fairly large FPGA, you could use the on-chip memory for a single-chip solution (well, not quite, some bus driver (level shifters) are likely to be needed).  Or a small FPGA plus one or two SRAM chips.

Assuming that you want any reasonable amount of memory (1MB or more),
a "fairly large FPGA" that provides it as on-chip memory costs several
*thousand* dollars.  It makes far more sense to use external memory,
and then you only need a tiny CPLD for control, or a small FPGA if you
want to implement ECC. Assuming that you run the programmable logic
and memory at 3.3V, the "level shifters" are just 74LVC245A
bidirectional buffers.

If I were going to do that, I'd use MRAM for the memory, so that it
would be nonvolatile (equivalent to the MK11 battery backup, which
supports power-fail restart).