Qbus split I&D?

Noel Chiappa jnc at mercury.lcs.mit.edu
Mon Mar 16 13:51:25 CDT 2015

    > From: Johnny Billquist

    > I need to see if I can locate the manual in the summer when I get close
    > to where I had that 11/34

That would be wonderful, if you find it! In addition to showing for sure how
it basically worked, I still also have a number of questions as to exactly
how it connected up to the optional cache, EUB memory, etc.

    > we still seem to talk about two different ENABLE products, though... :-)

I saying what I'm about to say, I am not in any way trying to be
argumentative (truly, I would be as happy if you were correct, just as much
as if I were, _provided that we had found out what the correct answer really
is_), but I really do think that your memory is playing tricks on you, with
the 'it didn't require any software changes at all'.

The "Enable/34" described in contemporary posts here:


works the way I'm describing... (Although note I do think Mike made some
mistakes in the diagram in the first one - I think the DMA devices have to be
behind the ENABLE/34, per his description in the second post of how it works.)

I wish we could find a copy of the paper mentioned there ("Modifications to
UNIX to Allow Four Mega Bytes of Main Memory on a 11/40 Class Processor" by
Clement T. Cole and Sterling J. Huxley), as it might also answer the questions
I have...


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