8-bit Computer TV Channel Use

[Alan Hightower]

On 2015-06-02 11:47, Mark J. Blair wrote: 

>> After that, you will need something fairly hefty at the start to find the characteristics of the signal and align the sampling. Then you just need to track clock drift and adjust a VCXO.
> 
> I was wondering whether I could get away with tracking the clock drift digitally rather than closing an analog PLL. What do you think?

For the general ADC route, I would put a PLL/clock synth on the board
in-case you have gross alignment errors on the incoming signal. The
input should be a multiple of 13.5 but you never know with clock
short-cuts on early systems. It's been a while since I've looked at the
Zynq PLLs, but usually they aren't designed for large bit depth M and
Ns. You will need one anyway to generate a 12.288 for audio and the
different output dot clocks. I've used TI CDCE906 and IDT's VersaClock
IIIs for this in other projects.

A VCXO is probably the simplest choice for clock recovery. Simple PWM
and RC filter to the tracking pin will allow you to slew the clock
150ppm or so.

As far as ZynQ, I would throw up a few warnings about the 300 MHz DLL
drop-out point on DDR3 and difficulty of routing. However I'm reminded
of the Zed board and their placement of by-pass caps in a pattern that
looked 'pretty'. Certainly not a beginner project, but you don't sound
like one. If you wanted to start with Parallella boards instead, I have
a couple trays of the SamTech mating connectors. I can send some your
way.

For SoC, it depends on the power you need to look at the signal. If I
were faced with the requirements you have created, I would start looking
at the Atmel SAMV7x line. The EVMs are starting to ship publicly and
it's the first to market for the ARM M7/Pelican core. It's has more DSP
performance in a small micro than most DSPs a generation ago. With OTG
and integrated highspeed USB PHYs, you could also ship the frame buffer
updates to a PC and support USB stick firmware update. Might be a nice
alternate solution to HDMI scaling. And it's super cheap. A number of
smaller FPGAs might do the trick depending on how complex your RTL
pipe-line is. The usual suspects, Spartan 6, MachXO2, and the new MAX10
from Altera.

-Alan