Multibus arbiter design

[Eric Smith]

Is anyone aware of any published detailed designs of Multibus
arbitration circuitry, NOT using the Intel bus arbiter chips (e.g.,
8218, 8219, 8289, 82289)? I know various vendors making Multibus CPU
cards for non-Intel CPUs (e.g., 68K or NS 32K) sometimes designed
their own arbiters out of TTL and/or PALs, but I haven't found any
schematics. The only thing I've found so far is an application note "A
Multibus Arbiter Design for 10 MHz Processors" in the 1988 AMD PAL
Device Handbook, but I'd like to see other examples.

I'm considering designing a Multibus I/O card that needs to be a bus
master, and while an 8289 or 82C89 would do what I want, they're
relatively hard to find and expensive, so I'd rather just do it in my
FPGA, with suitable buffering to meet the Multibus electrical specs.

It appears that the inner workings of the Intel 8289 arbiter are
documented in US patent 4,257,095.

The Intel MDS-800 circa 1975 used a bunch of TTL, but it was pretty
tightly intertwined with 8080-specific logic, and since the MDS-800
predated the Multibus spec and has a few obvious differences from it,
I don't think it serves as a particularly good bus arbiter design
example.