Reproducing old machines with newer technology (Re: PDP-12 at the RICM)

[tony duell]

> 
> I would modify that: if you take an existing design created by someone who doesn’t think about delay 
> differences, then the FPGA version won’t work.  Consider the 6600: at the speeds involved, you can’t 
> design in that sloppy fashion.  So there are multi phase clocks everywhere, with consecutive latch points 
> clocked by the consecutive phases.  That means that so long as the max latency is < the clock phase
> difference, it always works.

You are, of course, absolutely correct...

However, such designs are very few and far between. I will guess that if you took just about any of the 
discrete transistor or TTL-baased minis or desktops and fed the design straight into an FPGA compiler then
it will not work.

-tony