11/23 clock issue

[Pete Turnbull]

On 08/02/2015 11:20, Holm Tiffe wrote:
> Brent Hilpert wrote:

>> No you didn't. While the context of the discussion is testing and that may have been your intention, your comment specified no such qualification, and as such at best left it ambiguous/unclear.
>> Pete's comment was valid clarification and additional information (although I could have minor quibbles with some of the technical phrasing).
>
> You are simply wrong.

Ooh, somebody's still grumpy today.  Not me though, I'm writing this 
with a smile on my face :-)

> I'm answered in a thread reagarding a fault in a
> clock circuit of an PDP11 Processor Board, not in a discussion regarding
> the design of a new board with TTL cicuits.

Yet it will sit in the archive for years and since the message itself 
says nothing about that, it could easily be taken out of context by 
someone who knows less than you, I, or Brent.  Moreover, it doesn't 
always work as a reliable test, simply because there /are/ circumstances 
where letting an input float will sufficiently change the operating 
characteristics.

> Besides of that Petes sentence "TTL is supposed to have a 1K pullup (to
> limit possible transients); LSTTL can be directly connected to Vcc." above
> is plain wrong too.
> Direct me to a datasheet containing this please.

No, you're wrong.  Try looking in the Texas Instruments TTL Data Book; 
in the Fifth European Edition, it's clearly described on pages 5-4 to 
5-5.  It's also mentioned in chapter 3 of my 1971 edition of the Texas 
Instruments book "Designing with TTL Integrated Circuits", published by 
McGraw-Hill, which also has a lot to say about switching speeds, DC and 
AC noise margins, and noise rejection.  You might also care to read 
Chapter 9 especially section 9.06 "Some comments about logic inputs" in 
"Horowitz & Hill "The Art of Electronics" (one of the standard 
textbooks) culminating in their analysis of unused TTL inputs left open, 
and hence having /zero/ noise margin.

-- 
Pete

Pete Turnbull