Non-CRTC PET video circuitry...

[Josh Dersch]

Yet another "oh, let's spend an evening doing a small project" that's 
ballooned into a major undertaking:

I thought I'd try my hand at getting my old PET up and running again; 
this is an original "chiclet" keyboard model (with 6550 RAMs and no CRT 
Controller chip).  There are a multitude of problems with it (the CPU 
isn't resetting, I'm sure there's bad RAM and ROM) but I thought I'd 
start with the most obvious fault -- the video generation.

Here's a picture of what it's currently doing (sorry it's not very 
good...) : http://yahozna.dyndns.org/scratch/pet/oneline.jpg

It's only drawing a single line of characters (garbage with some noise 
due to a very terrible socket holding the character ROM), centered 
vertically.  I initially thought this was a VRAM addressing issue (a 
stuck counter or whatnot) but it turns out the VSync signal is much too 
fast -- it's only about 1.2ms long (it's supposed to be about 16ms).  
I'm actually surprised the monitor can deal with that without damage, so 
I've been leaving the monitor disconnected while debugging.  The HSync 
period is correct (63.8us or so), and most of the addressing / character 
display logic (which is driven by earlier portions of the video timing 
chain) seems to be running correctly, it's just only getting a chance to 
draw one line of characters before the next frame starts.

I'm not having much luck tracing down the fault; I have a schematic 
(http://www.zimmers.net/anonftp/pub/cbm/schematics/computers/pet/2001/320008-3.gif) 
but it's not making it easy to work out exactly how everything ties 
together.  I can't find anything resembling a service manual for this 
model, but perhaps I haven't looked hard enough yet.

The initial clock (output of E2 pin 6) is correct at 8Mhz; this is 
divided down to 2Mhz by the counter at C9 (pin 8, the divide by 4 
output), which is passed to the 74LS107 at C7 and from here it gets 
murky and I don't quite see how things fit.  I did replace C7 to no 
effect (ok, I jumped to conclusions...).  The divided clock outputs (Q, 
pins 3/2) from this have a period of about 256us; the LS107 at B6 
divides this down to the final period of 1.2ms which is used for the 
VSync signal.

Has anyone here any experience with this hardware?  Any tips?

Thanks,
Josh