pdp11/84 PMI memory: What is the problem with Q bus?
jnc at mercury.lcs.mit.edu
Fri Apr 24 11:43:31 CDT 2020
> From: Chris Zach
> Just checked the configuration and block mode DMA *is* off.
Interesting. So it's not bklock-mode on the QBUS which is screwed up, but
normal QBUS transfers. That jibes with the comment abour "gate array
incompatibilities" (which I take to mean "errors" :-).
> was the 11/70's MASSBUS channels nothing more than RH11-C's attached to
> the old FASTBUS on the 11/45 cpu core (which is what an 11/70 really
> is, with cache) or did they port right to the memory box?
RH70's are totally different from RH11's - a hex card, and a couple of quads
- and the interface to the /70's memory system is totally different from the
RH11's (which goes to the UNIBUS):
It has interfaces to both the cache, and the memory bus (although the diagram
in the 11/70 CPU handbook shows it as only connected to the cache).
I didn't follow the "the old FASTBUS on the 11/45 cpu core (which is what an
11/70 really is, with cache)"; the 70's cache is what's connected to what
used to be the FASTBUS, the memory bus connects to the cache, IIRC.
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