ISO: PDP-11/40 LTC and Stack Limit options
derschjo at gmail.com
Tue Nov 22 18:00:45 CST 2016
On 11/22/16 9:27 AM, Noel Chiappa wrote:
> > From: Josh Dersch derschjo at gmail.com
> > see if the same is true for other bus grants -- I can run the system
> > with no grant continuity card at all in slot 9 and everything works.
> Well, the BG4-BG7 grants definitely _are_ run through the SPC slot 9 (see
> below) - at least, on a stock system. It's _possible_ that the software
> you're loading doesn't use interrupts. (I have this vague memory that, unlike
> the -11/34, the /40 doesn't complain if there's a non-continuous grant line.)
> Or perhaps someone wired them across on that slot, to avoid knuckle-mashing
> trying to put a G727 down there.
Yes, I'd expect them to be run through the slot (though I expected the
NPG, too :)). And there does seem to be continuity between the BG pins
on the CPU backplane and those on the DD11.
If I remove the grant continuity card from slot 9, I can still boot
XXDP. If I remove a grant continuity card from the DD11 (with NPG still
intact), I can't -- it hangs as I'd expect with a hole in the grant chain.
No one's done anything cute like hard-wiring the grants in and there's
no evidence of any modifications. All expected voltages are present on
the backplane pins in the right places. I put a little contact cleaner
in the slot too, just in case. I still can't get an SLU to function in
that slot, though the CSR addresses seem to respond and the
console/diagnostic PROM chugs along happily when I power the machine up
(though nothing appears on the serial line).
Tonight I may try running the SLU on an extender board and verifying
that all the proper voltages are actually making it to the board. The
fact that the board appears to be responding but I'm getting nothing
over the serial line makes me think that maybe the -15V isn't present
for some reason...
> Anyway, the wire list in the drawings show all four lines (although they are
> listed in two places, under "BGx" and "BUS BGx"). E.g. BG4 is shown on pg. 79
> as going from D07E2 (Source - K4-6, pg. 63, top right) to D09S2 (which is the
> correct BG4 'in' pin for SPC), and as BUS BG4 on pg. 84 as going from D09T2
> (SPC BG4 'out' pin) to B09E2 (correct BG4 UNIBUS 'out' pin).
> > I now have the system booting XXDP
> > I did find out why there was that wire missing on the backplane; the
> > KW11-L requires a wire (carrying one of the bus grant signals) be
> > removed from slot 3.
> Right, BG6 is wired through that KW11-L slot because the clock needs
> interrupts - the wire list shows that on pg. 79, where the BG6 entry is longer
> than the other BGn entries, because of that. If I'm reading the notations
> correctly, it shows the jumper installed by default - I guess it was removed
> by hand on systems sold with a KW11-L?
The KW11-L manual suggests that this is the case, the installation
instructions specifically call out removing that wire. Apparently my
40's backplane had been reconfigured in such a manner at some point.
> There must also be some way to indicate that the jumper should be wired on
> top at both ends (so the F03V2 to D09M2 wire wouldn't have to be removed to
> pull the F03R2 to F03V2 jumper) - although maybe they just did _all_
> multi-pin runs as alternating low on both ends, high on both ends, repeat to
> make removal/replacement easier.
> Speaking of notation, dunno if you knew this (I didn't), but the wire list
> for the 11/40 includes etch also; you can tell etch entries from an 'H' in
> the "Q" column and 'P' in the "Remark" column. Don't confuse them with the
> 'H' in the "A/P" column, which also also has some 'L' entries; not sure what
> that is about, unless it tells whether the signal is asserted high or low.
That's useful information to have, thanks!
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