Honneywell multics? from panels. the inline phots in this message folks -smecc
jnc at mercury.lcs.mit.edu
Thu Mar 17 18:05:33 CDT 2016
> From: David Bridgham
> how the GE processor mapped each segment to physical memory on its own
> while the x86 maps the segments into a single 2^32 byte linear address
> space first and then maps that to physical memory.
Oh, right, I remember there was a 4GB limit on physical memory (which I
mentioned in an earlier message in this thread), but I'd forgotten the
The paging is done on that 4GB linear address space, so it's separate from
segmentation - on the 645 at least, the two are jumbled in together, which I
find over-complex. I like the clean separation between paging and segments.
> The x86 got this one wrong, in my opinion, as it means you can't have
> full-sized segments if you have more than one effective segment.
Well, but that's in the implementation, invisible to the user (in a properly
done OS). The user-visible architecture is 16K segments (8K local, 8K
global), of up to 4G each, or 2^46 total address space (per process).
Yes, not more than 4GB of them can be resident in memory at any one time, but
I'm not convinced that's a problem.
More information about the cctech