CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?
dkelvey at hotmail.com
Wed Jun 22 01:07:19 CDT 2016
I'll tell you a secret. I work for one of those two companies.
Processors are designed from such code, simulated and then
synthesized to silicon gates. I don't think that is too much of a
How the architecture is done is very much a secret. I can tell you that it is more complicated than one person can completely understand. It is a team effort with many people working from a general description of what each part does and how it should interact. Some work only on arrays while others work on floating point alu's and so on.
Each processor generation shares only a little with previous designs. To try to describe to someone outside how one of todays processor worked inside would require a book for each generation. Some parts are the same while other are vastly different.
It is interesting that I just read an article about the Chinese creating a faster supper computer. I suspect that many might think they did it with RISK design while most US made machines were stuck in CISC machines.
I don't have the real inside scoop but I can tell you what I think. Processors made today are general purpose. Floating point is a side function and not where the most emphasis is placed. I suspect that the Chinese designed the processors they used specifically to do floating point and were not the reuse of general purpose processors. The RISK/CISC is really not even relevant in todays processors since the main limiting factor is memory access bandwidth and effective use of caches. The instruction set used is only to deal with older software.
From: cctalk <cctalk-bounces at classiccmp.org> on behalf of ben <bfranchuk at jetnet.ab.ca>
Sent: Tuesday, June 21, 2016 11:53:20 AM
To: cctalk at classiccmp.org
Subject: Re: CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?
On 6/21/2016 9:47 AM, dwight wrote:
> One has to realize that all complex chips are done in Verilog or
> VHDL. Many old designs in processors can be re-implemented from
> timing and bus diagrams.
Where do you get this info? Most of the little stuff I have seen
it is still graphic layout and Intel (or IBM ...) is not going to
tell you their design style.
> This is no longer possible with todays processors like Intel or AMD
> processors. The complexity of possible sequential events are more
> than is practical to try to analyze from the pins.
> One can implement an instruction set but you'll never get close to
> the bus activity of current processors.
Who knows what secrets the cache holds?
> I would say that the most important part of either language is the
> ability to describe the time of simultaneous events. This is unlike
> most programs written in C or such. Of course, one can write a
> simulation language in C.
And a useless feature in my view. Real hardware has real delays
and simulation is prone errors translating to the real hardware.
PS: With the speed of modern transistors routing capacitance
and large die size; I think Vacuum tube/Drum memory might be better
model for modern computing.
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