CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?

Paul Koning paulkoning at
Tue Jun 21 11:24:23 CDT 2016

> On Jun 21, 2016, at 12:07 PM, Chuck Guzis <cclist at> wrote:
> On 06/21/2016 08:35 AM, Paul Koning wrote:
>> There are block diagrams, and those will have to serve if all else
>> fails, but that means reverse engineering the module level detail
>> (or, more precisely, constructing a functionally equivalent set of
>> module level details).  I keep hoping that some day the missing
>> details will be found.  Similarly, there are some other details that
>> are missing; the PPU wire lists predate the central/monitor exchange
>> jump feature so that too would have to be reconstructed from less
>> detailed information.
> Wasn't CEJ/MEJ a field-installable ECO?   Maybe there's paper on that
> somewhere.

Early on it may have been an ECO; later it became "standard option 10104 C/D".  An ECO document would certainly serve, but I haven't seen that either.

> ECS to me would be the real bugger, since it isn't just a box of core
> sitting off to the side.  On the Cybers, didn't it also include the ILR?
> That was too many years ago.  I do remember that it made the business
> of RCH/DCH much simpler in PPRES--no need to go through MTR.

I don't recognize "ILR".  The control for central exchange (XJ instruction) is is largely in the ECS coupler partly because some of the exchange package state (RAX/FLX/MA) lives there, as does the monitor mode flag.  Also partly because XJ and RE/WE are 01 opcodes that use the same address calculation.  I think once you get past the coupler into ECS itself and the ECS controller, there aren't any execution-related bits.  Not unless you count the Flag Register, which is a set of mutexes operated on by ECS read/write operations.


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