CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?

Toby Thain toby at
Mon Jun 20 15:41:12 CDT 2016

On 2016-06-20 4:35 PM, Paul Koning wrote:
>> On Jun 20, 2016, at 4:22 PM, Toby Thain <toby at> wrote:
>> On 2016-06-20 4:17 PM, Paul Koning wrote:
>>> ...A hardware model can
>> be used to replicate what old hardware did; for example, I have a
>> partial CDC 6600 model that shows how it boots, and that model includes
>> propagation delays on some signals (which are critical to correct
>> operation in certain spots).
>> This is probably of great interest to more than just me.
>> Any more details? Going to publish?
> Sure.  You can see it at svn://; ...
> Some day, if things go really well, this may result in a gate level accurate FPGA 6600.  I'm thinking I'll stop trying OCR and simply type the wire lists instead; that's likely to be faster in the long run.

This is frankly amazing. Thankyou for the details. Maybe one day I'll be 
able to volunteer some help. (Actually if there's anything I can do now, 
as an electronics noob but beginning student of digital logic & FPGA, 
let me know offlist.)


> 	paul

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