IDE knowledge anyone?

Warner Losh imp at
Mon Dec 7 17:47:12 CST 2015

On Mon, Dec 7, 2015 at 4:35 PM, Brad Parker <brad at> wrote:

> On 12/7/15 6:52 AM, Oliver Lehmann wrote:
> I don't have much to offer, but I have done PIO IDE accesses on lots of
> cpu's, including small ARM cpu's.  I would put the code into a "read loop"
> and "write loop" and look at the signals with a scope. Make sure they look
> good - i.e. clean edges and the width of the assertion is "ok".  I think
> the minimum is something like 300ns (I may be wrong, that's what I
> remember).   And make sure the address is stable before you assert WE# -
> I'd check that with a scope as well.  If you don't have a scope a simple
> logic analyser will work, but a scope is better.
> I seem to recall some drives got unhappy if some of the signals on the IDE
> interface were not exactly right - several need to be grounded and several
> pulled up with a resistor.  You don't mention what your physical interface
> is.  If you do I can dig up my notes and tell you what I've done in the
> past (not that it's authoritative, but it's something to compare with).

One thing that's often forgotten is that some IDE drives redefine what it
means to be low-end. The literature
is littered with stories of drive 'cost reduction' that would make the
original engineers cringe: removing filtering
caps because they weren't needed, removing termination and/or specifying
higher tolerance resistor packs
(which only breaks cables at the limits of the spec), using cheaper caps
that go horrifically bad over time
(both the electrolytic well known to this forum from power supplies, to
others that were cheap because
they were defective). If drive makers could save a buck doing it, you can
be sure at least one of them
has tried with product in the market that may be causing you grief. Things
that shouldn't matter most
of the time will matter. It might even be on your board. Too-slow rise
times, etc from board layout.

tl;dr: get a scope and make sure the signals look clean and meet the
minimums in the specs
by a safe margin.


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