Clearpoint DCME/Q4E configuration

Noel Chiappa jnc at
Thu Aug 20 08:12:59 CDT 2015

    > From: Johnny Billquist

    >> Yes, and if you plug one of their PMI memory boards into a Q/Q
    >> backplane, it will emit magic smoke, too! :-)

    > I don't remember if I've ever tried that

Don't! :-) As the MSV11-J manual puts it, "NOTE: Insertion of the MSV11-J in
a Q-Q backplane may damage other components or the memory itself. The PMI
bussing on the MSV11-J's CD connectors is not compatible with the +12V
bussing on the Q-Q backplane."

    > but I can believe that some jumpers would need to be moved around for a
    > Q-Q slot. ... No jumpers moved.

There are no jumpers to configure an MSV11-J for Q/Q slots. (It's only got 4
jumpers total, two of which are factory config; the others are battery backup

    > By CRC, I guess you mean ECC.

Yup, sorry, not completely awake when I typed that, I guess! :-)

    > And with 37 bits, I think it should have ECC. ECC depends on the CSR
    > address set correctly. But I could be wrong as well.

I think it needs more than 5 bits, for 32. The MSV11-J uses 6 bits, for

    >> However, when I plugged the other one in - nada. No response at all;
    >> the boot PROM bitched about 'no memory at 0'. So I'm not sure _what_
    >> that configuration is for.

    > Would sound like it was configured for a non-zero start address maybe?

I did wonder that, but why would anyone configure a 4MB card for a non-zero
start address?

Anyway, I have yet to investigate this jumper configuration more extensively
- later.

    > But if you tried with the switches/jumpers the same as on the board
    > working then it sounds like it would just be broken.

No, that board (mostly, except for the "Memory CSR" error) worked with the
jumpers in the _PMI_ configuration.  Although I suppose some of the circuitry
for use in the non-PMI config could be broken, but I think not. (More below.)

    >> The boot PROM was complaining about "Memory CSR Error" .. _but_ the
    >> memory was shown (by the boot PROM 'map' command) as PMI, and my own
    >> memory-test program showed it was all working OK.

    > And then the cards also have a CSR register or two, which is used for
    > various things. And they are expected to be at specific addresses.
    > ...
    > If you have a memory starting at address 0, there should be a CSR at a
    > specific address as well

So I did some experiments, with very interesting results. I took the card
that got the "Memory CSR Error", plugged it in, and ran a 'find all device
registers' program in the system with it in. It showed a single memory CSR,
at 172100. I then plugged in the card that _does_ pass the startup test, and
it also had a single register, at that same location.

So I guess it must be something about the way that register operates, that is
different between the two cards. Which is possible; as I mentioned, there are
a few programmable chips which are different revs. (And one large custom
chip, which _seems_ to be a different rev.)

Oddly enough, if I operate that 'broken' card in QBUS mode (after the CPU),
not PMI mode (before), it _does_ pass the built-in self-test!!!

Which argues that its failure to operate in QBUS mode, with the non-PMI
jumper settings, is not because the hardware to operate in QBUS mode is
broken. So I have no idea what the other set of jumper settings is for!

Blast, I sure wish we had documentation for these things!


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