UK PDP11 wanted
pete at dunnington.plus.com
Wed Apr 15 03:37:15 CDT 2015
On 14/04/2015 23:44, Johnny Billquist wrote:
> On 2015-04-14 23:16, Noel Chiappa wrote:
>> (1: Note that the MSV11-JB and -JC variants don't do QBUS properly,
>> and are
>> PMI only, and so can't be used in an 11/83. I seem to recall hearing it's
>> just QBUS block mode transfers that they don't do properly?)
I can't remember where, but I've seen that documented.
>> Which all does raise an interesting question: if an M8190 is in a
>> system with
>> a _mix_ of PMI and regular QBUS memory, do accesses to both memories work
>> fine? (E.g. if it's in a Q/CD backplane with a PMI board before it, and a
>> regular QBUS memory card after it.)
> As far as I know/understand, this will work just fine if you put the
> Qbus memory after the CPU and PMI memory before. I don't know what
> happens in general if you put Qbus memory before the CPU. That is
> another interesting question.
Yes, it does work with PMI before, and QBus after, the CPU. Yes, QBus
non-PMI memory does work (as QBus memory) if placed before the CPU. If
you put both in front of the CPU, obviously you put the QBus memory
higher up than the PMI memory, because it won't pass the PMI signals up
the bus if you do it the other way round. In other words, the PMI
memory must be the closest to the CPIU.
Putting QBus memory (or anything else that doesn't use the grant lines)
above the CPU is fine in a BA23 or BA123 system because the top three
(BA23) or four (BA123) slots have all the signals the CPU might want,
but in older systems there's a signal that only exists on slot 1: SRUN
L, on pin AF1 which is otherwise designated SSPARE2 and isn't bussed.
Lack of it in, say, slot 2, won't affect operation, but the RUN light
won't work :-) So many of my backplanes have SRUN L connected to slot
2, in much the same way as one might wire-wrap BDAL18-21 to upgrade 18
bits to 22. It makes it handy to put the CPU in slot 2 and some other
card in slot 1 for faultfinding.
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