Able ENABLE (was: Boot RXS)

Noel Chiappa jnc at mercury.lcs.mit.edu
Fri Jan 5 08:02:10 CST 2018


    >> From: Jim Stephens

    >> I had a meeting with Ken Omohundro on 12/7 and will be having dinner
    >> with him again soon. I'll ask him about it. I know he doesn't have any
    >> records left, but I could take him your notes and see what he recalls.

    > Thanks very much for that offer; we do think we know more or less how it
    > works 

So, I have completed what I think is a pretty thorough article on the CHWiki
about the ENABLE:

  http://gunkies.org/wiki/Able_ENABLE

It contains _everything_ I was able to glean from the still-extant
documentation, etc, which I have access to.

There is enough detail there to add support for it to SIMH/Ersatz-11 (hint,
hint :-).


    > there are two areas in which he might be able to help.

    > The first is some very low-level details of how it worked, in terms of
    > the UNIBUS interaction ... I _surmise_ that it was something like it
    > watches NPR/SACK for a DMA cycle .. then waits for BBSY to cycle, at
    > which point it knows it's a DMA cycle

Having refreshed my memory of how DMA cycles worked, I suspect it just watched
SACK and BBSY (since technically a UNIBUS device can do DMA cycles after
grabbing the bus with BRn), so no need to watch NPR.

    > The second is some details of how some of the optional stuff for using
    > existing memory, non-DMA devices, etc worked. ... I'll have to go
    > re-read the documentation

Having looked again, I don't think there's any mystery; probably I just hadn't
carefully read it before.

One question I do have, though: why the limit (per the documentation) to 128KB
of old memory? If I'm correcly understanding how the MemDap works (it
apparently makes the address space of the 'secondary' UNIBUS appear on top of
the EUB memory, on the EUB) it should be able to handle up to 248KB? (The top
8KB is the I/O space on the secondary UNIBUS, which, if devices on the
secondary UNIBUS are to be supported, must be visible to the CPU through the
ENABLE.)

    > It would also be interesting to know why he just didn't use a 3-bus
    > design .. I suspect that the answer is that they way they did it, they
    > could use a stock MUD backplane ... and only one over-the-back [UNIBUS]
    > connector into the ENABLE [there probably wasn't room for a second].

This too.


    >> I hope to get a biography and history of his companies including Able,
    >> and figure somewhere to get it stored.

    > The Computer History wiki would seem an ideal place for this sort of
    > content?

Reaction?

	Noel


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