Bug-for-bug compatibility [was RE: SimH DECtape vs. Tops-10 [was RE: Writing emulators [Was: Re: VCF PNW 2018: Pictures!]]]

Chuck Guzis cclist at sydex.com
Wed Feb 28 13:37:21 CST 2018

On 02/28/2018 10:55 AM, Paul Koning via cctalk wrote:

> In general, manuals are only a rough approximation of reality.  I
> remember an old joke that "PDP-11/x is compatible with PDP-11/y if
> and only if x == y".  And sure enough, if you look at the models
> appendix of the PDP-11 Architecture Handbook you will see cleary that
> this is true.  More precisely, it is if you ignore cases where two
> model numbers were assigned to the same thing, such as 11/35 and
> 11/40.
In general, I've always taken the manuals as saying "if you do things
the way we say they work, you'll be safe".   Where the manual says one
thing and the reality is otherwise, there's a cause for concern.

The arithmetic right-shift with sign extension always made perfect sense
to me on the 6600.  It's not so simple if all you have is a logical
right shift and want to do an arithmetic one.  The instruction mnemonic
reflects this (AX, vs. left shift LX).   If you've got the arithmetic
right shift and need a logical one with zero fill, add an MX to create a
mask and then a BX to clear the extended bits.  If you time your code,
the penalty is only 2 cycles.

I recall that we ran into trouble with trying to automatically take
advantage of the CMU option on the lower (72,73) CYBER machines (the
CYBER 74 didn't have the CMU option).  Since the CMU instructions
co-opted the no-op (46xxx) instruction, you could test for a CMU by
putting a 30 bit CMU instruction (IM) with the second parcel also being
46000 and a jump in the second two.

If there was no CMU, the first two parcels would be executed as no-ops
and the jump would be taken.  Otherwise, the CMU instruction would be
executed and no jump would occur, as CMU instructions could only be
placed in the first parcel of a word.   Clever--and I recall that it was
used in several libraries  (the lower CYBER CMU DM instruction was
faster than a CPU loop for block moves).

Then the CYBER 170 came along and someone decided that CMU instructions
attempted when there was no CMU should cause an "illegal instruction"
exception.   And then everything broke.

There, the code was playing by the book.   The reference manual shows
the lower 9 bits of the 46 instruction as shaded out; i.e., ignored. (on
the 6600, we found that they weren't exactly ignored--non-zero values
could affect the timing).

Later versions of the manual show the instruction encoding as 46000, but
that was only after CPD began taking advantage of the CMU capabilities
with the "trick".


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