KT-24 and/or -11/24 backplane info
jnc at mercury.lcs.mit.edu
Thu Jul 21 11:27:53 CDT 2016
So I'm trying to work out how the PDP-11/24 memory works - in particular, how
the memory slots in the backplane can also support SPC devices.
Chapter 5 of the -11/24 Technical Manual does not help - irritatingly! It
spends a lot of time talking about the CPU's memory mapping (well documented
elsewhere), and little on these blasted busses!
Alas, there seems to be no KT-24 prints online (although the tech manual makes
reference to various pages in it); prints of the backplane would also be
really useful, but again, don't seem to be in what is online. Does anyone have
Failing that, I guess it will require getting ahold of a backplane, and seeing
what I can find out with an ohm-meter.
In general, I am not absolutely positive about how the UNIBUS and the Extended
UNIBUS manage to co-exist on the backplane (although I think I have worked it
out - see below). The tech manual acts as if the KT-24 acts as an intermediary
between the two... which is fine, except that how are the both carried on the
backplane, separately, but at the same time?
When there _is_ a KT-24 (the system can work without one - more below on
this), how is the EUB (which is just the UNIBUS plus a couple of extra address
lines) separated from the UB? The way the UNIBUS mapping registers work, the
EUB address for any given cycle can vary from the UB address by an arbitrary
amount, so lower address bits can't be shared between the two busses.
(Because address bit X might have to simultaneously be '0' for one bus, and
'1' for the other.) I.e. the two busses can't somehow mostly share the same
pins, through some kludge...
It appears likely that somehow the UNIBUS is on connectors C-F (i.e. where it
normally is on SPC slots), and the EUB is on the A-B connectors (as in MUD
slots) - and the two are not connected together.
(Note that on the 11/24 backplane, 4 slots are marked "SPC/Mem", and two
"SPC/MUD", which supports this theory; the 4 slots would have the EUB and the
UB not connected together - as they would be in a normal MUD/SPC slot.)
Looking at the CPU prints (which _are_ available), it appears to confirm this
theory; the 22-bit EUB address bus is carried on the MUD/EUB address lines
(connectors A/B), and the 18-bit UNIBUS addresses are carried on the SPC
address pins (connector E). Dollars to donuts those pins are carried across
slots 1-6, and not intereconnected vertically (I have yet to verify that,
either with the backplane prints, or with an ohm-meter, but I would put a very
large bet on it.)
Oddly enough, the CPU uses the UNIBUS SPC data pins (connector C), instead of
the MUD ones (connector A). The thing is that EUB memory boards (e.g. MM11-M -
the relevant page of the MS11-P prints are missing from the online set, alas)
pick up the MUD pins for data. So the backplane must connect together the SPC
data pins and the MUD data pins.
The system can apparently also work _without_ a KT-24! Which raises the
question 'how do DMA devices get to the memory when there's no KT-24'?
>From looking at the CPU prints, (pg. K11) it _looks_ like the UNIBUS is
automagically mapped through to the EUB when there's no KT24 (there's a pin
which is apparently pulled low by the KT-24); the low (256-8=248) KB of UNIBUS
address space is mapped straight across to low address space on the EUB memory
With no KT24 in, a standard EUB memory can go in 2. Slot 2 is special, though;
the KT24 needs not just the UNIBUS lines, and EUB address lines (to map from
one to the other); it also has some special interconnects with the CPU, e.g.
that 'UNIBUS adapter present' line.
Guess I should document all this in the Computer History Wiki, but those prints
(KT-24, and -11/24 backplane) would still be useful.
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