Qbus split I&D?
hilpert at cs.ubc.ca
Tue Mar 17 14:46:19 CDT 2015
On 2015-Mar-17, at 12:27 PM, Paul Koning wrote:
>> On Mar 17, 2015, at 3:03 PM, Christian Gauger-Cosgrove <captainkirk359 at gmail.com> wrote:
>> On 16 March 2015 at 23:42, Eric Smith <spacewar at gmail.com> wrote:
>>> Not including parity or ECC, it takes two devices to fill the entire
>>> 4MB address space of the PDP-11/70. Either parity or ECC will require
>>> another one additional device, which won't be fully utilized.
>>> Ordinary SRAM is cheaper, but $110.16 for enough RAM chips to max out
>>> a PDP-11/70 doesn't seem all that expensive, unless you're comparing
>>> to DDR SDRAM DIMMs for PCs.
>> True, SRAM would be cheaper, and you can find faster SRAM and DRAM
>> than the currently available MRAM (if I recall correctly). But then
>> you lose the benefits of MRAM in the first place: It's non-volatile,
>> like core memory, and doesn't need battery backup (as you'd need if
>> you wanted to make SRAM "non-volatile").
> MRAM is non-volatile, sure. I’m not sure its write limit is high enough to be used as a substitute for main memory. In any case, what PDP-11 operating systems use the non-volatility of memory? I know of one: RSTS-11. But RSTS/E dropped that (it reboots on powerup instead). That makes sense, given that semiconductor memory appeared fairly early in the PDP-11 product life, and none of that came with battery backup. In other words, only some of the models in some configurations offered non-volatile memory, which made it fairly uninteresting for operating systems to support.
Well, even if the OSs didn't support restart, non-volatility of core was useful for retention of the bootstrap program on the front-panel/pre-boot-ROM machines, just so you didn't have to re-toggle the bootstrap at every power-up.
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