Hand-wired core for ROM?

Brent Hilpert hilpert at cs.ubc.ca
Sat Apr 11 01:58:10 CDT 2015

On 2015-Apr-10, at 3:23 PM, Noel Chiappa wrote:
>> From: Brent Hilpert
>> Core rope ROM has one magnetic core per the word-width of the memory.
>> That is, a memory of (say) 1024 16-bit words would have 16 cores.
> Not always (although your basic point, that in core ROM, a single core is
> often/usually used for more than one bit, is a very key point to note); the
> Apollo rope ROM had one core per 192 bits, or 12 words of 16 bits each,
> "thousands of ... cores" per memory rope. See:
>  http://web.mit.edu/digitalapollo/Digital%20Apollo%20Annotated.doc
> and there's a picture of one here:
>  http://klabs.org/mapld04/presentations/session_g/g1007_hall_s.ppt
> (see slide #15).
> Those notes do contain an interesting aside: "rearrange the program's
> fixed-memory allocations to avoid cases where such sets of 12 words contained
> too many ones to fit in their cores", which implies that the cores were
> fairly small, physically (since a one involved running the wire _through_ the
> core, not around it).
> I don't know why they didn't make the cores larger, and have fewer of them;
> my suspicion is that in manufacturing terms, it was easier to have more of
> them, with less wires through each one. (I can't think of an _electrical_
> reason to do so; unlike with RAM cores, where smaller cores are faster to
> switch, and take less power to do so.)

I recall seeing a partial description of the AGC ROM some time ago, with the diagram in the doc you link, but it didn't explain fully its relatively complex organisation, it would be interesting to study it further.

Coincidentally, I'm working on a Wang 520 right now, a descendant of the Wang 700 Rick mentioned, which uses a 2048-word * 42-bit core rope ROM for the microcontrol store. There can be over 1000 or 2000 address lines going through a given core.

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